Matthias Roell mrll

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• Joined on 2026-02-23

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SWE-Project

C++ 0 0

A project for the software engineering course from my university.

Updated 2026-02-23 14:14:09 +01:00

SimpleCPU

VHDL 0 0

A simple 8 Bit CPU-Design written in VHDL from a university course. Has some bugs.

Updated 2026-02-23 14:11:34 +01:00